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Draft:HILO HDL

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  • Comment: Possibly written with the help of LLM output; please address the fixes throughout the article and resubmit. Caleb Stanford (talk) 04:00, 12 May 2025 (UTC)
  • Comment: Were LLMs used to help generate this article? I am a bit worried about some of the text, particularly the content under "Features" and "Reception".
    For example:
    "Positive Aspects: Commentators praised HILO’s hierarchical approach and interactive debugging, noting that these features sped up verification cycles for complex digital systems."
    Please respond to the above, as it may mean the article could require increased scrutiny (see WP:LLM). In the meantime I will do a light review of a few things that need to be addressed. Caleb Stanford (talk) 03:53, 12 May 2025 (UTC)


HILO HDL (often referred to simply as "HILO") is an early hardware description language and logic simulation framework developed primarily in the late 1970s and early 1980s.[1] Designed to facilitate hierarchical, high-level modeling of complex digital circuits, HILO offered interactive simulation capabilities that influenced subsequent simulation tools and the evolution of standardized HDLs like VHDL and Verilog.[2]

History

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The development of HILO can be traced to efforts by researchers and engineers seeking a more efficient approach to simulate increasingly complex large-scale integrated (LSI) circuits.[3][4] Early work on HILO appears in the late 1970s under the auspices of several contributors, notably Peter Flake, Phil Moorby, and Simon Davidmann.[5] They introduced HILO as a "high-level interactive logic simulator," capable of modeling circuits at both the gate level and a more abstract behavioral level.[6]

By 1979–1980, the team released an enhanced version called “HILO-2", which expanded the language’s hierarchical modeling features and improved simulation efficiency.[7] Demonstrations at industry events such as the Design Automation Conference (DAC) generated interest among early adopters in academic and industrial R&D labs.[7] However, the lack of formal standardization and the eventual rise of VHDL (sponsored by the U.S. Department of Defense) and the evolution into Verilog (popularized by Gateway Design Automation) overshadowed HILO’s broader adoption in commercial EDA tool flows.[5]

The HILO project started in the UK in early 1970s (HILO-1)[1] and was commercialized at Brunel University in the 1980s (HILO-2[8][7]) and later by Cirrus Computers and finally by GenRad (HILO-3[9]). HILO-1 only had language constructs for modeling circuit's logical structure and was written in assembler.[1] HILO-2 extended the structural modeling and added the first Register Transfer Language (RTL) with timing and was written in the BCPL language.[7]

The HILO-2 project at Brunel had Peter Flake as the Technical Authority and Phil Moorby, Simon Davidmann, and others, working on the language and simulators.[7]

Features

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HILO[10][2] was one of the first commercial Hardware Description Languages used to describe and simulate electronics circuits and it was the basis for what became Verilog which has now evolved into SystemVerilog.[5]

HILO-2 had one language for electronic hardware description, and a different language for stimulus and simulator control.[5]

HILO-2 combined an interactive logic simulator with a hardware description language.[5] The HDL was completely declarative, consisting of a hierarchical netlist of multiple-levels of abstraction, primitive gates, and flip-flops, as well as configurable functions.[5][11] The simulator had an event driven kernel which was more efficient than the cycle-based approaches of that era and had a command line interface to interactively inspect, trace, and force signals to values and thereby making debugging efficient.[5][11] The HDL and simulator also had abstract higher level behavioral constructs on top of the standard gate-level constructs cutting time to model circuits.[5]

These capabilities differentiated HILO-2 from simpler netlist-driven simulators of the 1970s, offering early access to initial features of more advanced HDL paradigms that soon became industry standards.[7]

HILO-2 had two simulators - a fault-free logic simulator for exploring a designs behavior, and a fault simulator for simulating a design with faults injected to grade tests for functional board testing.[7]

Adoption and usage

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During the early 1980s, HILO-2 had a modest but notable presence in some UK universities for research, teaching and coursework such as Brunel University of London[12] and by early LSI design teams citing faster execution compared to older simulators such as Wang Laboratories.[11]

While HILO-2 and HILO-3 garnered a measure of recognition,[9] it never achieved the same level of industrial standardization as VHDL or Verilog.[10] Nevertheless, its advanced simulation concepts were recognized as helping shape the conversation around higher-level hardware modeling in the 1980s.[10]

In 1981 Prabhu Goel of Wang Laboratories in Massachusetts, United States, became the first U.S. customer of HILO-2[10][13] to be used in the design and verification of a 10,000 gate ASIC.

In 1982 Prabhu left Wang and set up what became Gateway and subsequently hired Phil Moorby who evolved the HILO-2 structural description syntax and keywords into Verilog with minor changes.[10][13]

Reception

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Reviews offered a mixed but generally positive view of HILO’s technical merit, praising its hierarchical approach and interactive debugging, noting that these features sped up verification cycles for complex digital systems and pointed out that the language lacked being an official open standard or broad EDA vendor support, limiting widespread adoption and long-term viability.[2]

By the mid-to-late 1980s, industry momentum had shifted significantly toward VHDL (standardized under IEEE 1076 in 1987) and Verilog (eventually IEEE 1364), leaving HILO primarily in niche use or academic reference.[10]

In 1984 HILO-2 was acquired by GenRad (General Radio) and the HDL was renamed GHDL (GenRad HDL) with the simulator being called HILO-3 and being re-written in C and ported to Unix.[10][13]

Ultimately Verilog became the HDL and simulator of choice in the industry and interest in HILO reduced.[10][13]

Legacy

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Despite its declining user base, HILO’s early emphasis on hierarchical and fast interactive logic simulation is often cited in historical analyses of HDL development and EDA tools. [2][5][10][11] Some of its concepts—particularly hierarchical modeling and event-driven simulation—would resurface in the mainstream adoption of high-level HDLs and advanced verification methodologies in the 1990s and beyond.[13]

Modern references to HILO[2][5][10][11][13] typically appear in retrospectives or textbook discussions of HDL evolution, listing it as one of the early pioneers in the development of hardware design languages.[5]

See also

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  • No official website known to remain; archival documents may be found in IEEE Xplore or at institutional libraries

References

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  1. ^ a b c Flake, P.L. (1975). "A digital Systems Simulator - HILO". Digital Processes. 1: 39–53.
  2. ^ a b c d e Dettmer, R. (2004). "The HILO inheritance". IEE Review. 50 (8): 22–26. doi:10.1049/ir:20040803 (inactive 11 March 2025).{{cite journal}}: CS1 maint: DOI inactive as of March 2025 (link)
  3. ^ Bell, C. Gordon; Newell, Allen (1971). "Possibilities for computer structures 1971". Proceedings of the May 16-18, 1972, spring joint computer conference on - AFIPS '72 (Spring). New York, New York, USA: ACM Press. p. 387. doi:10.1145/1479064.1479132.
  4. ^ Schorr, Herbert (December 1964). "Computer-Aided Digital System Design and Analysis Using a Register Transfer Language". IEEE Transactions on Electronic Computers. EC-13 (6): 730–737. doi:10.1109/pgec.1964.263907. ISSN 0367-7508.
  5. ^ a b c d e f g h i j k Flake, Peter; Moorby, Phil; Golson, Steve; Salz, Arturo; Davidmann, Simon (2020-06-12). "Verilog HDL and its ancestors and descendants". Proc. ACM Program. Lang. 4 (HOPL): 87:1–87:90. doi:10.1145/3386337.
  6. ^ "A brief history of logic simulation". Semiconductor Engineering. Retrieved 2025-04-01.
  7. ^ a b c d e f g Harris, R. L.; Davidmann, S. J.; Musgrave, G. (1984-01-01), Wexler, Joanna (ed.), "HILO-2 - A SYSTEM TO BUILD ON", CAD84, Butterworth-Heinemann, pp. 48–60, ISBN 978-0-408-01440-3, retrieved 2025-01-04
  8. ^ Davidmann, Simon (1981). "HILO-2 team members".
  9. ^ a b Wharton, David (1983). "Introduction to the HILO-3 Logic Simulator" (PDF).
  10. ^ a b c d e f g h i j Newton, Richard (2005). "Presentation of the 2005 Phil Kaufman Award to Phil Moorby".
  11. ^ a b c d e Moorby, Phil (April 22, 2013). "An Oral History of Phil Moorby, Creator of Verilog". Computer History Museum. Archived from the original on April 1, 2025. Retrieved April 1, 2025.
  12. ^ Palnitkar, Samir (February 21, 2003). "Verilog HDL: A Guide to Digital Design and Synthesis" (PDF). d1.amobbs.com. Archived from the original (PDF) on 2024-06-14. Retrieved 2025-05-13.
  13. ^ a b c d e f Sutherland, Stuart; Davidmann, Simon; Flake, Peter (2006). SystemVerilog for design: a guide to using SystemVerilog for hardware design and modeling (2nd ed.). New York, NY: Springer. ISBN 978-0-387-33399-1.
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